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d a t a sh eet product speci?cation supersedes data of 2003 may 07 2003 sep 04 integrated circuits 74lvc00a quad 2-input nand gate
2003 sep 04 2 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a features 5 v tolerant inputs for interfacing with 5 v logic wide supply voltage range from 1.2 to 3.6 v cmos low power consumption direct interface with ttl levels inputs accept voltages up to 5.5 v complies with jedec standard no. 8-1a esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. specified from - 40 to +85 c and - 40 to +125 c. description the 74lvc00a is a high-performance, low-power, low-voltage, si-gate cmos device, superior to most advanced cmos compatible ttl families. inputs can be driven from either 3.3 or 5 v devices. this feature allows the use of these devices as translators in a mixed 3.3 and 5 v environment. schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall times. the 74lvc00a provides the 2-input nand function. quick reference data gnd = 0 v; t amb =25 c; t r =t f 2.5 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . function table see note 1. note 1. h = high voltage level; l = low voltage level. symbol parameter conditions typical unit t phl /t plh propagation delay na, nb to ny c l = 50 pf; v cc = 3.3 v 2.1 ns c i input capacitance 4.0 pf c pd power dissipation capacitance per gate v cc = 3.3 v; notes 1 and 2 15 pf input output na nb ny llh lhh hlh hhl
2003 sep 04 3 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a ordering information pinning type number package temperature range pins package material code 74lvc00ad - 40 to +125 c 14 so14 plastic sot108-1 74lvc00adb - 40 to +125 c 14 ssop14 plastic sot337-1 74lvc00apw - 40 to +125 c 14 tssop14 plastic sot402-1 74LVC00ABQ - 40 to +125 c 14 dhvqfn14 plastic sot762-1 pin symbol description 1 1a data input 2 1b data input 3 1y data output 4 2a data input 5 2b data input 6 2y data output 7 gnd ground (0 v) 8 3y data output 9 3a data input 10 3b data input 11 4y data output 12 4a data input 13 4b data input 14 v cc supply voltage
2003 sep 04 4 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a handbook, halfpage 00 mna210 1 2 3 4 5 6 7 1a 1b 1y 2a 2b 2y gnd v cc 4b 4a 4y 3b 3a 3y 14 13 12 11 10 9 8 fig.1 pin configuration so14 and (t)ssop14. handbook, halfpage 114 1a v cc 7 2 3 4 5 6 1b 1y 2a 2b 2y 13 12 11 10 9 4b 4a 4y 3b 3a 8 gnd 3y mna950 gnd (1) top view fig.2 pin configuration dhvqfn14. (1) the die substrate is attached to this pad using conductive die attach material. it can not be used as a supply pin or input. handbook, halfpage mna212 1y 1a 3 1b 1 2 2y 2a 6 2b 4 5 3y 3a 8 3b 9 10 4y 4a 11 4b 12 13 fig.3 logic symbol. handbook, halfpage mna246 3 & & & & 2 1 6 5 4 8 10 9 11 13 12 fig.4 logic symbol (ieee/iec).
2003 sep 04 5 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a handbook, halfpage mna211 a b y fig.5 logic diagram (one gate). recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so14 packages: above 70 c derate linearly with 8 mw/k. for ssop14 and tssop14 packages: above 60 c derate linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 c derate linearly with 4.5 mw/k. symbol parameter conditions min. max. unit v cc supply voltage for maximum speed performance 2.7 3.6 v for low-voltage applications 1.2 3.6 v v i input voltage 0 5.5 v v o output voltage 0 v cc v t amb operating ambient temperature - 40 +125 c t r ,t f input rise and fall times v cc = 1.2 to 2.7 v 0 20 ns/v v cc = 2.7 to 3.6 v 0 10 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +6.5 v i ik input diode current v i <0 -- 50 ma v i input voltage note 1 - 0.5 +6.5 v i ok output diode current v o >v cc or v o <0 - 50 ma v o output voltage note 1 - 0.5 v cc + 0.5 v i o output source or sink current v o =0tov cc - 50 ma i cc , i gnd v cc or gnd current - 100 ma t stg storage temperature - 65 +150 c p tot power dissipation t amb = - 40 to +125 c; note 2 - 500 mw
2003 sep 04 6 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a dc characteristics at recommended operating conditions; voltages are referenced to gnd (groun d=0v). symbol parameter test conditions min. typ. (1) max. unit other v cc (v) t amb = - 40 to +85 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.2 -- v i o = - 12 ma 2.7 v cc - 0.5 -- v i o = - 18 ma 3.0 v cc - 0.6 -- v i o = - 24 ma 3.0 v cc - 0.8 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 -- 0.2 v i o =12ma 2.7 -- 0.4 v i o =24ma 3.0 -- 0.55 v i li input leakage current v i = 5.5 v or gnd 3.6 - 0.1 5 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 3.6 - 0.1 10 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o = 0 2.7 to 3.6 - 5 500 m a
2003 sep 04 7 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a note 1. all typical values are measured at v cc = 3.3 v and t amb =25 c. t amb = - 40 to +125 c v ih high-level input voltage 1.2 v cc -- v 2.7 to 3.6 2.0 -- v v il low-level input voltage 1.2 -- gnd v 2.7 to 3.6 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 100 m a 2.7 to 3.6 v cc - 0.3 -- v i o = - 12 ma 2.7 v cc - 0.65 -- v i o = - 18 ma 3.0 v cc - 0.75 -- v i o = - 24 ma 3.0 v cc - 1 -- v v ol low-level output voltage v i =v ih or v il i o = 100 m a 2.7 to 3.6 -- 0.3 v i o =12ma 2.7 -- 0.6 v i o =24ma 3.0 -- 0.8 v i li input leakage current v i = 5.5 v or gnd 3.6 -- 20 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 3.6 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 0.6 v; i o = 0 2.7 to 3.6 -- 5000 m a symbol parameter test conditions min. typ. (1) max. unit other v cc (v)
2003 sep 04 8 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a ac characteristics gnd = 0 v; t r =t f 2.5 ns. notes 1. typical value is measured at v cc = 3.3 v. 2. skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. ac waveforms symbol parameter test conditions min. typ. max. unit waveforms v cc (v) t amb = - 40 to +85 c t phl /t plh propagation delay na, nb to ny see figs 6 and 7 v cc = 1.2 - 12 - ns v cc = 2.7 1.0 2.4 5.1 ns v cc = 3.0 to 3.6 1.0 2.1 (1) 4.3 ns t sk(0) skew note 2 v cc = 3.0 to 3.6 -- 1.0 ns t amb = - 40 to +125 c t phl /t plh propagation delay na, nb to ny see figs 6 and 7 v cc = 1.2 --- ns v cc = 2.7 1.0 - 6.5 ns v cc = 3.0 to 3.6 1.0 - 5.5 ns t sk(0) skew note 2 v cc = 3.0 to 3.6 -- 1.5 ns handbook, halfpage mna218 t phl t thl t tlh t plh v m v m na, nb input ny output gnd v i v oh v ol fig.6 the input na, nb to output ny propagation delays. v m = 1.5 v at v cc 3 2.7 v; v m = 0.5v cc at v cc < 2.7 v. v ol and v oh are typical output voltage drop that occur with the output load.
2003 sep 04 9 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a handbook, full pagewidth open gnd 50 pf 2 v cc v cc v i v o mna368 d.u.t. c l r t r l 500 w r l 500 w pulse generator s1 fig.7 load circuitry for switching times. v cc v i t plh /t phl 1.2 v v cc open 2.7 v 2.7 v open 3.0 to 3.6 v 2.7 v open definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2003 sep 04 10 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m q a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
2003 sep 04 11 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a unit a 1 a 2 a 3 b p cd (1) e (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 1.25 0.2 7.9 7.6 1.03 0.63 0.9 0.7 1.4 0.9 8 0 o o 0.13 0.1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. sot337-1 99-12-27 03-02-19 (1) w m b p d h e e z e c v m a x a y 1 7 14 8 q a a 1 a 2 l p q detail x l (a ) 3 mo-150 pin 1 index 0 2.5 5 mm scale ssop14: plastic shrink small outline package; 14 leads; body width 5.3 mm sot337-1 a max. 2
2003 sep 04 12 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
2003 sep 04 13 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area a c c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
2003 sep 04 14 philips semiconductors product speci?cation quad 2-input nand gate 74lvc00a data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r20/05/pp 15 date of release: 2003 sep 04 document order number: 9397 750 11929

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